As technology nodes continue to shrink, circuit operations become increasingly more sensitive to process and environmental conditions. As a result, semiconductor chips become increasingly more susceptible to design-related yield loss, which is often caused by the flawed design of sensitive circuits, such as analog circuits. The verification of the chip-design thus becomes more important.
FIG. 1 illustrates a conventional flow for verifying chip-designs. Typically, the chip-designs are provided using files with a commonly-known graphic data system (GDS) format (block 2). Design rule check (DRC) and electrical rule check (ERC) are performed at full-chip level for capturing basic design errors (block 4). Next, the GDS files are converted to netlists (block 6) that can be used by simulation tools, such as special programs for interactive circuit elements (SPICE). SPICE simulations are then performed on the netlists to check for the performance of the circuits (block 8).
The conventional chip-verification schemes suffer from drawbacks. The DRC and ERC checks can only be used for checking basic operation correctness. They are not suitable for verifying sensitive analog circuits. Since SPICE simulations need exhaustive simulations, input patterns, and design disciplines for schematics and layouts, to accurately determine the extent of problems in a typical analog circuit, literally millions of SPICE iterations may need to be performed, which requires a great amount of input vectors and corner conditions. Conventionally, the SPICE simulations were only performed on the circuit blocks in the chip instead of the entire chip, often because full-chip SPICE simulations are too complicated and too time consuming. Although simplified assumptions can be made to reduce the number of SPICE iterations, the simplification may result in significant flaws in analog circuit not being captured.
It is to be realized that the chip-verifications are performed in non-ideal environments. Various situations may occur during the chip-verifications, including: designers failing to follow common design practices or best known methods (BKMs); IP-level checking being performed without taking neighboring circuits into consideration; schematic and layout designs being performed by different groups of people because of the needed specific expertise; the SPICE simulations being performed improperly; and key parameters being omitted in extractions/simulations. These situations may result in the further degradation in the quality of the chip-verifications. New methods and systems for performing chip-verifications with improved efficiency and improved quality are thus needed.